`timescale 1ns / 1ps

module vivada_fifo_tb ();

    reg             clk_50m;
    reg             rst_n;
    wire    [16:0]  sum;

    initial begin
        clk_50m = 0;
        rst_n   = 0;
        #100 rst_n =1;
    end

    always #10 clk_50m = ~clk_50m;

    vivada_fifo inst_vivada_fifo (
        .clk_50m                (clk_50m),
        .rst_n                  (rst_n),
        .sum                    (sum)
    );

endmodule
